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BBD Delay

DSP related issues, mathematics, processing and techniques

BBD Delay

Postby Tepeix » Tue Feb 15, 2022 1:23 am


Here's a sort of BBD Delay.
Based on some (maybe false ?) assumptions i made on them.

It's mono or the same delay for all channel for now.
(But the code must be really different to support different delays)

The BBD (in my assumptions) is a clock then a read write memory.
I don't even know if there's some interpolation between sample ?
But the clock change speed and the sample rate of the delay.

So this code use a ramp osc that skip the read write process until it reach max.
(Could be maybe better with a loop 2 or up-sampled)
The more the delay is long the more it will be un-sampled.

Here's the code :
Code: Select all
streamin in;
streamin speed;
streamout out;
float mem[4096];
float saw=0;
int index=0; int step=-16;
int max=65535;
movaps xmm0,saw;
addps xmm0,speed;
cvtps2dq xmm1,xmm0;
cvtdq2ps xmm1,xmm1;
subps xmm0,xmm1;
movaps saw,xmm0;
movd eax,xmm1;
cmp eax,0;
jz go;
movaps xmm0,index;
paddd xmm0,step;
andps xmm0,max;
movaps index,xmm0;
movd eax,xmm0;
movaps xmm0,mem[eax];
movaps out,xmm0;
movaps xmm0,in;
movaps mem[eax],xmm0;

What do you think about this BBD concept ?
BBD concept v2.fsm
Little edit : comment in code to change delay max time.
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